As the geometry of transistors with respect to technology in integrated circuits (microelectronic chips or micro chips) shrinks, the number and type of defects on a chip may increase exponentially with an increase in logic density. A defect may be an error introduced into a device during the manufacturing process. A fault model is a mathematical description of how a defect alters design behavior. During the design of the integrated circuit, testing is performed to ensure that the integrated circuit works as anticipated. Testing of integrated circuits may be facilitated by design techniques known in the art as Design For Test (DFT), also known as Design for Testability. Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPG) is an electronic design automation (EDA) technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. Design for testability (DFT) based on scan and automatic test pattern generation (ATPG) were developed to explicitly test each gate and path in a design.
Scan Shift power and power droop during scan shifting pose major challenges to the test process as more gates are integrated within an area in shrinking nanometer nodes. As such, there is the need for Q-gating (“gated q” design). Q-gating is a DFT for reducing power consumption during shift operations. A Q-gated design adds logic gates to the circuit design between the q-output of each scan flip flop and the cone of logic. A shift line to the logic gates is asserted during shift operations. Assertion of the shift line causes output from the logic gates to the cone of logic to be held in a single state during shift operations. As such, the q-output of each scan flip flop is designated as the one to be “gated” during shift mode. However, there may be problems with using Q-gating to control scan-shift power for the entire design.